Tutorial

How to Perform RF Yield Analysis

RF yield analysis predicts what fraction of manufactured units will meet specification. Step-by-step procedure using Monte Carlo simulation, statistical tools, and design optimization.

What Is Yield Analysis?

Manufacturing yield is the percentage of assembled units that meet all RF specifications. Component tolerances (±5% inductor, ±10% capacitor, ±0.05mm PCB trace) cause each unit to have slightly different performance. Yield analysis — most commonly Monte Carlo simulation — predicts this distribution before committing to production.

Step 1: Define Yield Criteria

  Yield Pass/Fail Criteria (example LTE Band 8 matching network):
  ✓ S11 < −10 dB at 880–915 MHz (TX band)
  ✓ S11 < −10 dB at 925–960 MHz (RX band)
  ✓ S21 > −0.8 dB at band center (IL < 0.8 dB)

  A unit PASSES only if ALL three conditions are simultaneously met.
  This is the "yield specification" — define it before running Monte Carlo.

Step 2: Assign Component Tolerances

ComponentStandard TolerancePremium Tolerance
SMD Inductor 0402±5%±2% (special order)
SMD C0G Capacitor±5% (standard), ±0.5 pF (small C)±1%
PCB trace width±0.05 mm (standard PCB)±0.025 mm (controlled-impedance)
X7R Capacitor±20% (also temperature-dependent)±10%

Step 3: Run Monte Carlo in RF View

  1. Build circuit: DUT S2P + matching network in Circuit Simulator
  2. Switch to Tolerance Analysis tab
  3. Set each component's tolerance percentage
  4. Choose N = 500 runs (sufficient statistical accuracy)
  5. Tap "Run" → RF View generates 500 randomized circuits and simulates all

Step 4: Compute Yield

  From 500 Monte Carlo runs:
  Count traces meeting ALL pass criteria:
    Pass (S11<−10dB in TX AND RX, IL<0.8dB): 463 of 500

  Yield = 463 / 500 = 92.6%

  Statistical confidence (95% CI for 463/500):
  Lower bound: 89.9%, Upper bound: 94.8%

  Target: Yield ≥ 90% → 92.6% passes ✓
  If yield < 90%: redesign (lower Q, tighter tolerance components)

Step 5: Sensitivity Analysis

  Run isolated tolerances to find which component limits yield:
  Fix all components at nominal, vary only L1: yield = 98.1%
  Fix all, vary only C1: yield = 95.2%
  Fix all, vary only PCB trace W: yield = 99.4%

  Conclusion: C1 is the most critical component → tighten to ±2%
  After change: overall yield improves from 92.6% to 96.3%
RF View Yield Analysis: Monte Carlo, sensitivity analysis, and visual spread plots — all in RF View's Tolerance Analysis tab. Free on Android. No additional simulation license needed.

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